The present invention relates to semiconductor device fabrication and integrated circuits and, more specifically, to structures for spacers in a device structure for a field-effect transistors and methods for forming spacers in a device structure for a field-effect transistor.
Device structures for a field-effect transistor include a source, a drain, a channel situated between the source and drain, and a gate structure including a gate electrode and a gate dielectric separating the gate electrode from the channel. A gate voltage applied to the gate electrode is used to provide switching that selectively connects the source and drain to each another through the channel. The channel of a planar field-effect transistor is located beneath the top surface of the substrate on which the gate structure is supported.
A fin-type field-effect transistor (FinFET) is a type of field-effect transistor that is capable of being more densely packed in an integrated circuit than planar field-effect transistors. A FinFET may include a semiconductor fin, an gate electrode that overlaps a channel in the semiconductor fin, and heavily-doped source/drain regions formed in sections of the semiconductor fin peripheral to the gate structure. The channel of a FinFET is effectively elevated above the top surface of the substrate so that the gate structure can wrap about multiple sides of the channel. The wrapped-arrangement between the gate electrode and fin improves control of the channel and reduces the leakage current when the FinFET is in its ‘off’ state. This, in turn, enables the use of lower threshold voltages and results in better performance and power.
Spacers may be formed adjacent to the sidewalls of the gate electrode with properties intended to boost device performance. A bi-layer spacer that includes an inner spacer proximate to the sidewalls and an outer spacer separated from the sidewalls by the inner spacer. The inner spacer may be selected to have a lower dielectric constant than the outer spacer, which tends to boost circuit speed but also tends to reduce its robustness. The outer spacer may be selected to resist processes that can cause spacer erosion and to thereby protect the inner spacer against erosion. For example, the etch rate of the outer spacer may be several times lower than the etch rate of the inner spacer when exposed to, for example, dilute hydrofluoric acid. If the protection afforded by the outer spacer fails, the inner spacer can erode and lead to the formation of avoid that links the gate electrode and the source/drain region normally separated from the gate electrode by the bi-layer spacer.
Improved structures for spacers in a device structure for a field-effect transistor and methods for forming spacers in a device structure for a field-effect transistor are needed.